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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
FEATURES
* Three banks of outputs: 1 bank of 2 LVDS outputs and 2 banks of 1 LVPECL output * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended reference clock input * 4 independently selectable output frequency on each bank: 318.7MHz, 212.5MHz, 159.375MHz and 106.25MHz * Maximum output frequency: 318.75MHz * Crystal input frequency: 25.5MHz * VDDO_LVPECL can be set for 3.3V or 2.5V, allowing the device to generate 3.3V or 2.5V LVPECL levels * RMS phase jitter at 106.25MHz, using a 25.5MHz crystal (637KHz to 10Mhz intergration): 4.82ps (typical)
GENERAL DESCRIPTION
The ICS843404 is a low phase noise Fibre Channel Clock Generator and is a member of the HiPerClockSTM HiPerClockSTM family of high performance clock solutions from ICS. The device provides two banks of 1 LVPECL output per bank and one bank of 2 LVDS outputs. Each bank can be independently set by using their respective frequency select pins for the following output frequencies: 318.75MHz, 212.5MHz, 159.375MHz or 106.25MHz, using a 25.5MHz 18pF parallel resonant crystal. The ICS843404 can also be driven from a 25.5MHz singleended reference clock. For system debug or test purposes, the PLL can be bypassed using the VCO_SEL pin.
ICS
PIN ASSIGNMENT
MR VCO_SEL VDDo_LVDS LVDS0 nLVDS0 LVDS1 nLVDS1 nc LVPECL_FSELB0 LVPECL_FSELB1 nc VDDA LVPECL_FSELA0 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LVDS_FSEL0 LVDS_FSEL1 VDDO_LVPECL LVPECLA0 nLVPECLA0 LVPECLB0 nLVPECLB0 XTAL_SEL TEST_CLK GND GND XTAL_IN XTAL_OUT LVPECL_FSELA1
* Phase noise @ 106.25MHz Offset Noise Power 100Hz ................. -84.6 dBc/Hz 1KHz ................. -105.7 dBc/Hz 10KHz ................. -122.3 dBc/Hz 100KHz ................. -125.9 dBc/Hz * Supply voltage modes: * VDD = VDDA = 3.3V * VDDO_LVPECL = 3.3V or 2.5V * VDDO_LVDS = 3.3V * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial termperature information available upon request
ICS843404
28-Lead TSSOP, 173-MIL 4.4mm x 9.7mm x 0.92mm body package G Package Top View
BLOCK DIAGRAM
VCO_SEL Pullup
LVPECL_FSELA1:0
VDDO_LVPECL
00 01 10 11 0 0 00 01 10 11
/2 /3 /4 /6 /2 /3 /4 /6
LVPECLA0 nLVPECLA0
TEST_CLK Pulldown
25.5MHz
LVPECL_FSELB1:0
LVPECLB0 nLVPECLB0
XTAL_IN XTAL_OUT XTAL_SEL Pullup
OSC
1
Phase Detector
VCO 637.5MHz
(Fixed)
1
LVDS_FSEL1:0
LVDS0 nLVDS0
M = 25 (fixed)
00 01 10 11
/2 /3 /4 /6
LVDS1 nLVDS1 MR Pulldown
VDDO_LVDS
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843404AG www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2004
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Type Description Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs LVPECLx/LVDSx to go low and the Pulldown inver ted outputs nLVPECLx/nLVDSx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. VCO select pin. When HIGH, PLL is enabled. When LOW, PLL is in Pullup Bypass mode. LVCMOS/LVTTL interface levels. Output supply pin for LVDS outputs. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. No connect. Frequency select pin for LVPECLB outputs. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pin for LVPECLB outputs. See Table 3B. Pullup LVCMOS/LVTTL interface levels. Analog supply pin. Frequency select pin for LVPECLA outputs. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Frequency select pin for LVPECLA outputs. See Table 3B. Pullup LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Pullup Reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number Name
1
MR
Input
2 3 4, 5 6, 7 8, 11 9 10 12 13 14 15 16, 17 18, 19 20 21 22, 23
VCO_SEL VDDO_LVDS LVDS0, nLVDS0 LVDS1, nLVDS1 nc LVPECL_FSELB0 LVPECL_FSELB1 VDDA LVPECL_FSELA0 VDD LVPECL_FSELA1 XTAL_OUT, XTAL_IN GND TEST_CLK XTAL_SEL
Input Power Output Output Unused Input Input Power Input Power Input Input Power Input Input
nLVPECLB0, Output Differential output pair. LVPECL interface levels. LVPECLB0 nLVPECLA0, Ouput Differential output pair. LVPECL interface levels. 24, 25 LVPECLA0 26 VDDO_LVPECL Power Output supply pin for LVPECL outputs. LVDS_FSEL1, Frequency select pins for LVDS outputs. See Table 3A. Input Pulldown 27, 28 LVDS_FSEL0 LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
843404AG
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REV. A JUNE 16, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
LVDS Output Frequency (MHz) (25.5MHz Crystal) 318.75 (default) 212.5 159.375 106.25
TABLE 3A. LVDS FREQUENCY SELECT FUNCTION TABLE
Inputs LVDS_FSEL1 0 0 1 1 LVDS_FSEL0 0 1 0 1 LVDS Output Divider 2 3 4 6
TABLE 3B. LVPECLA0 FREQUENCY SELECT FUNCTION TABLE
Inputs LVPECL_FSELA1 0 0 1 1 LVPECL_FSELA0 0 1 0 1 LVPECLA0 Output Divider 2 3 4 6 LVPECLA0 Output Frequency (MHz) (25.5MHz Crystal) 318.75 212.5 159.375 (default) 106.25
TABLE 3C. LVPECLB0 FREQUENCY SELECT FUNCTION TABLE
Inputs LVPECL_FSELB1 0 0 1 1 LVPECL_FSELB0 0 1 0 1 LVPECLB0 Output Divider 2 3 4 6 LVPECLB0 Output Frequency (MHz) (25.5MHz Crystal) 318.75 212.5 159.375 (default) 106.25
843404AG
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REV. A JUNE 16, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V 50mA 100mA 10mA 15mA 49.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVPECL Outputs) Continuous Current Surge Current Outputs, IO (LVDS Outputs) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. LVPECL POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, VDDA = 2.9V TO 3.465V, TA = 0C TO 70C
Symbol VDD VDDA VDDO_LVPECL IDD IDDA IDDO_LVPECL Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 2.9 3.135 Typical 3.3 3.3 3.3 TBD TBD TBD Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVPECL POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDA = 2.9V TO 3.465V, VDDO = 2.5V5%,
TA = 0C TO 70C Symbol VDD VDDA VDDO_LVPECL IDD IDDA IDDO_LVPECL Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 2.9 2.375 Typical 3.3 3.3 2.5 TBD TBD TBD Maximum 3.465 3.465 2.625 Units V V V mA mA mA
TABLE 4C. LVDS POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, VDDA = 2.9V TO 3.465V, TA = 0C TO 70C
Symbol VDD VDDA VDDO_LVDS IDD IDDA IDDO_LVDS
843404AG
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current
Test Conditions
Minimum 3.135 2.9 3.135
Typical 3.3 3.3 3.3 TBD TBD TBD
Maximum 3.465 3.465 3.465
Units V V V mA mA mA
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REV. A JUNE 16, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, VDDA = 2.9V TO 3.465V,
TA = 0C TO 70C
Symbol Parameter VIH Input High Voltage VCO_SEL, XTAL_SEL, LVPECL_FSELA0:F_SELA1, Input LVPECL_FSELB0:F_SELB1 Low Voltage LVDS_FSEL0:F_SEL1, MR TEST_CLK TEST_CLK, MR, LVPECL_FSELA0, LVPECL_FSELB0, Input LVDS_FSEL0, LVDS_FSEL1 High Current LVPECL_FSELA1, LVPECL_FSELB1, VCO_SEL, XTAL_SEL TEST_CLK, MR, LVPECL_FSELA0, LVPECL_FSELB0, Input LVDS_FSEL0, LVDS_FSEL1 Low Current LVPECL_FSELA1, LVPECL_FSELB1, VCO_SEL, XTAL_SEL
Test Conditions
Minimum Typical 2 -0.3 -0.3
Maximum VDD + 0.3 0. 8 1.3 150
Units V V V A
VIL
VDD = VIN = 3.465V,
IIH
VDD = VIN = 3.465V,
5
A
VDD = 3.465V, VIN = 0V,
-5
A
IIL
VDD = 3.465V, VIN = 0V,
-150
A
TABLE 4E. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, VDDA = 2.9V TO 3.465V,
TA = 0C TO 70C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VDDO - 1.4 VDDO - 2.0 0.6 Typical Maximum VDDO - 0.9 VDDO - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VDDO - 2V.
TABLE 4F. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, VDDA = 2.9V TO 3.465V, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 4 1.35 5 Maximum Units mV mV V mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pf parallel resonant crystal.
843404AG
Test Conditions
Minimum
Typical Maximum 25.5 50 7
Units MHz pF
Fundamental
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Test Conditions Minimum Typical 15 TBA 318.75MHz (12KHz - 20MHz) 5.64 2.82 5.77 4.82 1 20% to 80% 400 212.5MHz (1.274MHz - 20MHz) 159.375MHz (12k - 20MHz) 106.25MHz (637KHz - 10MHz) Maximum 318.75 Units MHz ps ps ps ps ps ps ms ps %
TABLE 6A. LVPECL AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, VDDA = 2.9V TO 3.465V, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Bank Skew; NOTE 1 Output Skew; NOTE 2, 3 RMS Phase Jitter, (Random); NOTE 4 PLL Lock Time Output Rise/Fall Time
tsk(b) tsk(o)
tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew within a bank of ourputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross point. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Please refer to the Phase Noise Plots.
TABLE 6B. LVPECL AC CHARACTERISTICS, VDD = 3.3V5%, VDDA = 2.9V TO 3.465V, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Bank Skew; NOTE 1 Output Skew; NOTE 2, 3 318.75MHz (12KHz - 20MHz) RMS Phase Jitter, (Random); NOTE 4 PLL Lock Time Output Rise/Fall Time 20% to 80% 212.5MHz (1.274MHz - 20MHz) 159.375MHz(12k - 20MHz) 106.25MHz (637KHz - 10MHz) tL tR / tF 15 TBA 5.03 2.73 4.60 3.96 1 400 50 Test Conditions Minimum Typical Maximum 318.75 Units MHz ps ps ps ps ps ps ms ps %
tsk(b) tsk(o)
tjit(O)
odc Output Duty Cycle See NOTES 1 through 4 above.
TABLE 6C. LVDS AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, VDDA = 2.9V TO 3.465V, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Bank Skew; NOTE 1 Output Skew; NOTE 2, 3 318.75MHz (12KHz - 20MHz) RMS Phase Jitter, (Random); NOTE 4 PLL Lock Time Output Rise/Fall Time 20% to 80% 212.5MHz (1.274MHz - 20MHz) 159.375MHz(12k - 20MHz) 106.25MHz (637KHz - 10MHz) tL tR / tF 15 TBA 4.25 4.19 4.30 3.78 1 350 50 Test Conditions Minimum Typical Maximum 318.75 Units MHz ps ps ps ps ps ps ms ps %
tsk(b) tsk(o)
tjit(O)
odc Output Duty Cycle See NOTES 1 through 4 above.
843404AG
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REV. A JUNE 16, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Fibre Channel Filter 106.25MHz
RMS Phase Jitter (Random) 637KHz to 10MHz = 4.82ps (typical)
TYPICAL PHASE NOISE AT 106.25MHZ FOR LVPECL
0 -10 -20 -30 -40 -50
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 10 100 1k 10k -160
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
100k 1M 10M 100M
TYPICAL PHASE NOISE AT 106.25MHZ FOR LVDS
0 -10 -20 -30 -40 -50
Fibre Channel Filter 106.25MHz
RMS Phase Jitter (Random) 637KHz to 10MHz = 3.78ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k
843404AG
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OFFSET FREQUENCY (HZ) Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
REV. A JUNE 16, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VDD, VDDA, VDDO
Qx
SCOPE
Qx
SCOPE
3.3V5% Power Supply Float GND + -
LVPECL
nQx
LVDS
nQx
GND
-1.3V0.165V
LVPECL 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2V 2.8V0.04V
Phase Noise Plot
Noise Power
VDD, VDDA, VDDO
Qx
SCOPE
LVPECL
GND
nQx
Phase Noise Mask
-0.5V0.125V
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nLVPECLx, nLVDSx LVPECLx, LVDSx nLVPECLy, nLVDSy LVPECLy, LVDSy
nLVPECLx, nLVDSx LVPECLx, LVDSx
Pulse Width t PERIOD
tsk(o)
OUTPUT SKEW
843404AG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
nLVPECLA0
80%
LVPECLA0 nLVPECLB1 LVPECLB1
80% LVDS VOD 20% tF
Clock Outputs
20% tR
tsk(b)
LVPECL BANK SKEW
nLVDS0
80%
LVDS0 nLVDS1 LVDS1
80% LVPECL VSW I N G 20% tF
Clock Outputs
20% tR
tsk(b)
LVDS BANK SKEW BANK SKEW (MAXIMUM
VALUE)
OUTPUT RISE/FALL TIME
VDD
VDD out
out
DC Input
LVDS
100
VOD/ VOD out
DC Input
LVDS
out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
843404AG
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843404 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10F 24
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843404 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25.5MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 18p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS843404
Figure 2. CRYSTAL INPUt INTERFACE
843404AG
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ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near
3.3V
LVDS_Driv er
+
R1 100
-
100 Ohm Differiential Transmission Line 100 Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
TERMINATION
FOR
3.3V LVPECL OUTPUT
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
Zo = 50
125
3.3V 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT FIN
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
50 VCC - 2V RTT
84 84 Zo = 50
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843404AG
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ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VDD - 2V. For VDDO = 2.5V, the VDDO - 2V is very close to
2.5V
2.5V
VDDO=2.5V
2.5V
VDDO=2.5V
R1 250
R3 250
Zo = 50 Ohm
+
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL Driv er
Zo = 50 Ohm
-
-
2,5V LVPECL Driv er
R2 62.5
R1 50
R2 50
R4 62.5
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VDDO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
843404AG
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ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
resonant 25.5MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
LAYOUT GUIDELINE
Figure 6 shows a schematic example of the ICS843404. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel
VDDO
U1
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
LVDS_FSEL0 MR LVDS_FSEL1 VCO_SEL VDDO_LVDS VDDO_LVPECL LVPECLA0 LVDS0 nLVPECLA0 nLVDS0 LVPECLB0 LVDS1 nLVPECLB0 nLVDS1 XTAL_SEL nc LVPECL_FSELB0 TEST_CLK LVPECL_FSELB1 GND nc GND VDDA XTAL_IN LVPECL_FSELA0 XTAL_OUT VDD LVPECL_FSELA1
ICS843404
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Zo = 50
+
Zo = 50
R2 50
X1
R1 50
R7 24
C5 0.1u
25.5 MHz
R3 50
C1 18pF
C2 22pF
C3 10u
C4 0.1u
Zo = 50
+
R4 100
Zo = 50
-
(U1,3)
C6 0.1u
VDDO
(U1,26)
C7 0.1u
VDD = 3.3V VDDO = 3.3V
FIGURE 6. ICS843404 SCHEMATIC EXAMPLE
843404AG
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ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
68.7C/W 43.9C/W
500
60.5C/W 41.2C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
82.9C/W 49.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843404 is: 2314
843404AG
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ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
28 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 9.60 6.40 BASIC 4.50 Millimeters Minimum 28 1.20 0.15 1.05 0.30 0.20 9.80 Maximum
Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html
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843404AG
REV. A JUNE 16, 2004
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Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Package 28 Lead TSSOP 28 Lead TSSOP on Tape and Reel 28 Lead "Lead Free" TSSOP 28 Lead "Lead Free" TSSOP on Tape and Reel Count 48 per tube 1000 48 per tube 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843404AG ICS843404AGT ICS843404AGLF ICS843404AGLFT Marking ICS843404AG ICS843404AG ICS843404AGLF ICS843404AGLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843404AG
www.icst.com/products/hiperclocks.html
16
REV. A JUNE 16, 2004

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